NU32v2: A Detailed Look at Programming the PIC32
** This page is under construction and is not complete. KML 1/17/2011. **
After you have programmed your PIC32 for the first time and verified that you can create a new project, compile it, and run it on your NU32v2, it is useful to take a step back and understand the basics of the programming process, beginning with a PIC32 fresh from the factory. We will do that on this page. We will begin by discussing the virtual memory map of the PIC32. To discuss the virtual memory map, it is useful to know hexadecimal (hex, or base 16) notation, where each digit of a hex number takes one of 16 values, 0...9, A...F. Since 16 = 2^4, a single hex digit represents four digits of a number written in binary (base 2). The table below gives examples.
| Hex | Binary | Base 10 |
| 7 | 0111 | 7 |
| D | 1101 | 13 |
| B5 | 1011 0101 | 181 |
To distinguish hex and binary numbers from base 10 numbers, we begin the numbers with 0x and 0b, respectively. For example, 0xA9 = 10*16^1 + 9*16^0 = 0b10101001 = 1*2^7 + 0*2^6 + 1*2^5 + 0*2^4 + 1*2^3 + 0*2^2 + 0*2^1 + 1*2^0 = 160 = 1*10^2 + 6*10^1 + 0*10^0. The 0x and 0b conventions are also used in the C language.
The PIC32 Virtual Memory Map
The PIC32 has a virtual memory map consisting of 4 GB (four gigabytes, or 2^32 bytes, where each byte equals 8 bits) of addressable memory. All memory regions reside in this virtual memory space at their unique respective addresses. This includes program memory (flash), data memory (RAM), peripheral special function registers (SFRs), and configuration registers (e.g., bits that control the the system clock period and other functions). For example, the peripheral SFRs begin at virtual memory location 0xBF800000 and end at virtual memory address 0xBF8FFFFF. Subtracting the begin address from the end address, and adding one byte, we get 0x100000, which is 1*16^5 = 1,048,576, commonly written as 1 MB. (Note: Section 3 of the reference manual has the calculation as 4 KB, so either the end address or the calculation is wrong in the reference manual. I believe it is the calculation that is wrong.)
In addition to this virtual memory map, there is also a physical memory map. When you are writing a program, you only deal with the virtual memory map. The PIC implements a Fixed Mapping Translation (FMT) unit that takes the virtual memory address and maps it to a physical memory address. In other words, the virtual memory address is translated to a set of bit values on an addressing bus that allows the PIC's CPU to address the appropriate peripheral, flash memory location, RAM location, etc. We will focus on the virtual memory map, since our goal is to program the PIC.
Virtual memory is partitioned into two types of address space: user address space (the lower 2 GB) and kernel address space (the upper 2 GB). By analogy to your computer, the kernel address space is to hold the computer's operating system, while the user address space is to hold a program that runs under the operating system. This is for safety: the user's program should not interfere or compromise the operating system, i.e., it shouldn't be able to overwrite data that the operating system needs to function. We will not be using an operating system, so our programs will reside in the kernel address space.
What does the partitioning? bootloader?
The kernel virtual address space contains two subsections: one that is cacheable and one that is not. "Cacheable" means that ... fill in here.
The three major partitions of PIC32 virtual memory, then, are called KSEG0, KSEG1, and USEG/KUSEG, where KSEG0 corresponds to the cacheable kernel address space, KSEG1 corresponds to the non-cacheable kernel address space, and USEG/KUSEG corresponds to the user address space. The "K" in this last name indicates that programs in the kernel can address the user address space. Programs in the user address space cannot address the kernel address space.
Each of KSEG0, KSEG1, and USEG/KUSEG are further broken into the following sections: data RAM, program RAM, and program flash.
The noncacheable KSEG1 is further broken into the following segments: RAM, flash, peripheral SFRs, and boot flash. The cacheable KSEG0 has almost the same segments (and indeed the same physical memory addresses), except it lacks a peripheral SFR segment, as the SFRs are noncacheable. USEG/KUSEG is partitioned into RAM and flash segments. The virtual memory addresses are
| Start Address | Size (bytes) | Partition | Kind | Notes |
|---|---|---|---|---|
| 0x7D000000 + BMXPUPBA | BMXPFMSZ - BMXPUPBA | USEG/KUSEG | program flash | |
| 0x7F000000 | BMXDUPBA - BMXDUDBA | USEG/KUSEG | data RAM | |
| 0x7F000000 | BMXDRMSZ - BMXDUPBA | USEG/KUSEG | program RAM | |
| 0x80000000 | BMXDKPBA | KSEG0 (cacheable) | data RAM | same physical address as KSEG1 data RAM |
| 0x80000000 + BMXDKPBA | BMXDUDBA - BMXDKPBA | KSEG0 (cacheable) | program RAM | same physical address as KSEG1 program RAM |
| 0x9D000000 | BMXPUPBA | KSEG0 (cacheable) | program flash | same physical address as KSEG1 program flash |
| 0xA0000000 | BMXPUPBA | KSEG1 | data RAM | |
| 0xA0000000 + BMXDKPBA | BMXDUDBA - BMXDKPBA | KSEG1 | program RAM | |
| 0xBD000000 | BMXPUPBA | KSEG1 | program flash | |
| 0xBF800000 | 1 MB | kernel | peripheral SFRs | peripherals are non-cacheable |
| 0xBFC00000 | 12 KB | kernel | boot flash |
can execute from data memory; configure the BMX registers (p35 of RM) to run code from RAM or set up User mode partition. CPU reset address is 0xBFC00000.
FMT to physical memory. as programmer, only need to know virtual.
