Difference between revisions of "555 Timer"
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Symbol for the 555 timer: [[Image:555_symbol.gif]] |
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==Basic Operation== |
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Connection diagram for the 555 IC timer (click for larger image). |
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[[Image:555_symbol.png|400 px]] |
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See the [[media:LM555.pdf|Datasheet for the LM555]] for more information and example applications/circuits. |
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The output of a 555 timer is either ''high'' (close to +V<sub>CC</sub>) or ''low'' (close to GND). |
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Inside the 555 timer is a voltage divider the divides +V<sub>CC</sub> into thirds. A voltage comparator compares the '''trigger''' input (pin 2) with 1/3 V<sub>CC</sub>, and another comparator compares the '''threshold''' (pin 6) with 2/3 V<sub>CC</sub>. The point at 2/3 V<sub>CC</sub> on the voltage divider is connected to the '''control voltage''' (pin 5). This pin can be used to modify the values of 1/3 V<sub>CC</sub> and 2/3 V<sub>CC</sub> without having to change V<sub>CC</sub>. However, if this input is not going to be used, it should be grounded through a bypass capacitor (0.01uF) to protect it from noise. |
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The 555 timer also has a flip-flop, which is controlled by the two comparators and the '''reset''' input. |
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The '''trigger''' and '''reset''' inputs are level-sensitive [[Digital#Active_Low_Input|active low]] inputs. To activate the trigger, the voltage on the ''trigger'' pin must be pulled down to under 1/3 V<sub>CC</sub>. The trigger experiences a delay when changing states so it should be returned to ''high'' at least 10μs before the end of the timing cycle or else the cycle will be immediately re-triggered. |
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To reset the timer, the voltage on the ''reset'' pin must be pulled under 0.4V. The ''reset'' input will override other inputs and set the '''output''' (pin 3) to ''low''. If the ''reset'' input is not going to be used, it should be wired to V<sub>CC</sub> to prevent false signals. |
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In its initial state (assuming ''threshold'' is ''low'' and ''trigger'' is ''high''), the 555 timer's internal flip-flop connects the '''discharge''' (pin 7) to the ground and sets the output to ''low''. Each time the trigger voltage is pulled down under 1/3 V<sub>CC</sub>, the flip-flop will break the ''discharge'' pin's connection to ground, and set the output to ''high''. It will hold this state until something (usually a capacitor) forces the ''threshold'' pin's voltage equal to 2/3 V<sub>CC</sub>, which will reset the flip-flop. |
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==Monostable and Astable mode== |
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The 555 family of timer chips can be used in either '''monostable''' mode or '''astable''' mode. In the monostable or "one shot" mode, each time the 555 timer is triggered, the output will go ''high'' for a specified amount of time, then return to ''low'' and await another trigger signal. In the astable mode, the timer triggers itself periodically and becomes an oscillator, sending out a train of pulses. |
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===Monostable Mode=== |
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Connections for the 555 timer in monostable mode: |
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[[Image:555_monostable.gif]] |
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The circuit operates as follows: |
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#In this circuit's initial condition, the capacitor ''C'' is held discharged through the ''discharge'' pin, which is grounded through the flip-flop in the timer. The ''threshold'' voltage is equal to the voltage across the capacitor. |
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#When the ''trigger'' pin receives a negative trigger pulse less than 1/3 V<sub>CC</sub>, the flip-flop sets the ''output'' to high and disconnects the ''discharge'' pin from the ground. This allows the capacitor to charge until the voltage across it reaches 2/3 V<sub>CC</sub>, which takes about '''t=1.1R<sub>A</sub>C seconds'''. |
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#When the ''threshold'' voltage reaches 2/3 V<sub>CC</sub>, the flip-flop resets, connecting ''discharge'' to the ground and setting ''output'' to ''low''. It is now back in the initial state, and awaits another trigger pulse. |
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By selecting the resistor and capacitor, the length of the output pulse can be controlled. If the trigger receives a signal while the output is still ''high'', there is no effect. This circuit can be used for [[Switch_Debouncing|debouncing]]. |
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Timing diagram for the 555 in monostable mode: |
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[[Image:monostable_timing.gif]] |
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===Astable mode=== |
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In the ''astable'' mode, the circuit will keep re-triggering itself, resulting in a pulse train. The circuit for the 555 in astable mode looks like this: |
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[[Image:555_astable_circuit.gif]] |
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In this case, the capacitor charges and discharges between 1/3 V<sub>CC</sub> and 2/3 V<sub>CC</sub>. The 555's output will the ''high'' while charging, and ''low'' while discharging. The capacitor charges and discharge at different rate—it has to charge through R<sub>A</sub> and R<sub>B</sub>, but it only discharges through R<sub>B</sub>. |
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Thus, we can adjust the length of the output's highs and lows by adjusting these resistors. |
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The length of a ''output high'' is equal to: |
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<math>t_{high}=0.693(R_A+R_B)C\,</math> |
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The length of a ''output low'' is equal to: |
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<math>t_{low}=0.693(R_B)C\,</math> |
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Each '''period''' consists of an ''output high'' and ''output low'', so the total period is equal to: |
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<math>T=t_{high}+t_{low}=0.693(R_A+2R_B)C\,</math> |
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and the '''frequency''' is: |
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<math> f=\frac{1}{T}=\frac{1.44}{(R_A+2R_B)C}</math> |
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The '''duty cycle''', often expressed as a percentage, is defined as the length of the pulse divided by the length of the period: |
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<math>D=\frac{t_{high}}{T}</math> |
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The timing diagram for the 555 in astable mode: |
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[[Image:555_astable_timing.gif]] |
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==References== |
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[http://www.national.com/ds/LM/LM555.pdf LM555 Datasheet.] |
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van Roon, Tony. ''555 Timer Tutorial'''. 5 July 2006. [http://www.uoguelph.ca/~antoon/gadgets/555/555.html http://www.uoguelph.ca/~antoon/gadgets/555/555.html]. |
Latest revision as of 18:23, 4 August 2006
Basic Operation
Connection diagram for the 555 IC timer (click for larger image).
See the Datasheet for the LM555 for more information and example applications/circuits.
The output of a 555 timer is either high (close to +VCC) or low (close to GND).
Inside the 555 timer is a voltage divider the divides +VCC into thirds. A voltage comparator compares the trigger input (pin 2) with 1/3 VCC, and another comparator compares the threshold (pin 6) with 2/3 VCC. The point at 2/3 VCC on the voltage divider is connected to the control voltage (pin 5). This pin can be used to modify the values of 1/3 VCC and 2/3 VCC without having to change VCC. However, if this input is not going to be used, it should be grounded through a bypass capacitor (0.01uF) to protect it from noise.
The 555 timer also has a flip-flop, which is controlled by the two comparators and the reset input.
The trigger and reset inputs are level-sensitive active low inputs. To activate the trigger, the voltage on the trigger pin must be pulled down to under 1/3 VCC. The trigger experiences a delay when changing states so it should be returned to high at least 10μs before the end of the timing cycle or else the cycle will be immediately re-triggered.
To reset the timer, the voltage on the reset pin must be pulled under 0.4V. The reset input will override other inputs and set the output (pin 3) to low. If the reset input is not going to be used, it should be wired to VCC to prevent false signals.
In its initial state (assuming threshold is low and trigger is high), the 555 timer's internal flip-flop connects the discharge (pin 7) to the ground and sets the output to low. Each time the trigger voltage is pulled down under 1/3 VCC, the flip-flop will break the discharge pin's connection to ground, and set the output to high. It will hold this state until something (usually a capacitor) forces the threshold pin's voltage equal to 2/3 VCC, which will reset the flip-flop.
Monostable and Astable mode
The 555 family of timer chips can be used in either monostable mode or astable mode. In the monostable or "one shot" mode, each time the 555 timer is triggered, the output will go high for a specified amount of time, then return to low and await another trigger signal. In the astable mode, the timer triggers itself periodically and becomes an oscillator, sending out a train of pulses.
Monostable Mode
Connections for the 555 timer in monostable mode:
The circuit operates as follows:
- In this circuit's initial condition, the capacitor C is held discharged through the discharge pin, which is grounded through the flip-flop in the timer. The threshold voltage is equal to the voltage across the capacitor.
- When the trigger pin receives a negative trigger pulse less than 1/3 VCC, the flip-flop sets the output to high and disconnects the discharge pin from the ground. This allows the capacitor to charge until the voltage across it reaches 2/3 VCC, which takes about t=1.1RAC seconds.
- When the threshold voltage reaches 2/3 VCC, the flip-flop resets, connecting discharge to the ground and setting output to low. It is now back in the initial state, and awaits another trigger pulse.
By selecting the resistor and capacitor, the length of the output pulse can be controlled. If the trigger receives a signal while the output is still high, there is no effect. This circuit can be used for debouncing.
Timing diagram for the 555 in monostable mode:
Astable mode
In the astable mode, the circuit will keep re-triggering itself, resulting in a pulse train. The circuit for the 555 in astable mode looks like this:
In this case, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. The 555's output will the high while charging, and low while discharging. The capacitor charges and discharge at different rate—it has to charge through RA and RB, but it only discharges through RB.
Thus, we can adjust the length of the output's highs and lows by adjusting these resistors.
The length of a output high is equal to:
The length of a output low is equal to:
Each period consists of an output high and output low, so the total period is equal to:
and the frequency is:
The duty cycle, often expressed as a percentage, is defined as the length of the pulse divided by the length of the period:
The timing diagram for the 555 in astable mode:
References
van Roon, Tony. 555 Timer Tutorial'. 5 July 2006. http://www.uoguelph.ca/~antoon/gadgets/555/555.html.