https://hades.mech.northwestern.edu//index.php?action=history&feed=atom&title=Quadrature_decoding_in_hardware%2C_or_just_counters 2026-05-18T04:53:53Z Revision history for this page on the wiki MediaWiki 1.43.8 https://hades.mech.northwestern.edu//index.php?title=Quadrature_decoding_in_hardware,_or_just_counters&diff=5676&oldid=prev 2007-12-26T03:26:03Z

<p></p> <p><b>New page</b></p><div>Some encoders produce up to a million counts per revolution. For very fast quadrature signals there is no way that a software quadrature decoder can avoid overrun errors. Instead we may use the LS7083 chip to translate the A and B quadrature signals into brief pulses indicating up-count or down-count. The up and down counts can be configured as external input signals to increment counter/timer 0 and counter/timer 1 respectively. No ISR is required, one simply reads the timer counts whenever required.<br /> <br /> In the example code QuadratureHard.c, the counter/timers are read every 10mS. They are both 16-bit counters, so they roll over from 65535 to 0. To assemble a single 32-bit encoder count variable called bigcount, we add on the recent up-counts from Timer 0 and subtract the recent down-counts from Timer 1. If either Timer has decreased in value, it must be due to a rollover, and bigcount is corrected by 65536.</div>

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