NU32v2: Digital Input and Output - Revision history

Lynch at 11:22, 16 January 2016

2016-01-16T11:22:50Z

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			'''THIS PAGE REFERS TO A PRE-RELEASE VERSION OF THE NU32 PIC32 DEVELOPMENT BOARD. FOR INFORMATION, SAMPLE CODE, AND VIDEOS RELATED TO THE PRODUCTION VERSION (2016 AND LATER), AND TO THE CORRESPONDING BOOK "EMBEDDED COMPUTING AND MECHATRONICS WITH THE PIC32 MICROCONTROLLER," VISIT [[NU32\|THE NU32 PAGE]].'''

	Digital inputs and outputs (DIO) are the simplest of interfaces between the PIC and other electronics, sensors, and actuators. The PIC32 has many DIO pins, each of which can take one of two states: high or low.		Digital inputs and outputs (DIO) are the simplest of interfaces between the PIC and other electronics, sensors, and actuators. The PIC32 has many DIO pins, each of which can take one of two states: high or low.

Lynch: /* Details */

2011-01-27T16:56:28Z

Details

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	* '''ODCx''': <tt>ODCB = 0x00FF</tt> configures RB0..RB7 as open drain, and pins RB8..RB15 as typical buffered output. An individual pin can be referenced as ODCBbits.ODCB8, for example.		* '''ODCx''': <tt>ODCB = 0x00FF</tt> configures RB0..RB7 as open drain, and pins RB8..RB15 as typical buffered output. An individual pin can be referenced as ODCBbits.ODCB8, for example.

	* '''CNPUE''': The relevant bits of this SFR are CNPUE<21:0>, and they apply only to the 22 change notification pins CN0..CN21. If CNPUEbits.CNPUE2 = 1, then the pin with CN2 function has the internal pull-up resistor enabled, and if CNPUEbits.CNPUE2 = 0, then it is disabled. The command <tt>CNPUE = ~~0xFFFFFF~~</tt> enables the internal pull-up resistors for all CN pins. The default has the pull-ups disabled.		* '''CNPUE''': The relevant bits of this SFR are CNPUE<21:0>, and they apply only to the 22 change notification pins CN0..CN21. If CNPUEbits.CNPUE2 = 1, then the pin with CN2 function has the internal pull-up resistor enabled, and if CNPUEbits.CNPUE2 = 0, then it is disabled. The command <tt>CNPUE = 0xFFFFF</tt> enables the internal pull-up resistors for all CN pins. The default has the pull-ups disabled.

	Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB \|= 0x0001</tt>, but the former is faster.		Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB \|= 0x0001</tt>, but the former is faster.

Lynch at 16:53, 27 January 2011

2011-01-27T16:53:06Z

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	* '''CNPUE''': The relevant bits of this SFR are CNPUE<21:0>, and they apply only to the 22 change notification pins CN0..CN21. If CNPUEbits.CNPUE2 = 1, then the pin with CN2 function has the internal pull-up resistor enabled, and if CNPUEbits.CNPUE2 = 0, then it is disabled. The command <tt>CNPUE = 0xFFFFFF</tt> enables the internal pull-up resistors for all CN pins. The default has the pull-ups disabled.		* '''CNPUE''': The relevant bits of this SFR are CNPUE<21:0>, and they apply only to the 22 change notification pins CN0..CN21. If CNPUEbits.CNPUE2 = 1, then the pin with CN2 function has the internal pull-up resistor enabled, and if CNPUEbits.CNPUE2 = 0, then it is disabled. The command <tt>CNPUE = 0xFFFFFF</tt> enables the internal pull-up resistors for all CN pins. The default has the pull-ups disabled.

	Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB ^= 0x0001</tt>, but the former is faster.		Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB \|= 0x0001</tt>, but the former is faster.

	Other SFRs and their functions are described in Chapter 12 of the Reference Manual. The C names of the SFRs, and the structures with their bit references, can be found in the file p32mx795f512l.h, which is under pic32-libs/include/proc. The SET, CLR, and INV registers are described in Section 2 of the Reference Manual.		Other SFRs and their functions are described in Chapter 12 of the Reference Manual. The C names of the SFRs, and the structures with their bit references, can be found in the file p32mx795f512l.h, which is under pic32-libs/include/proc. The SET, CLR, and INV registers are described in Section 2 of the Reference Manual.

Nelson Rosa: /* Details */

2011-01-27T16:38:08Z

Details

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	* '''AD1PCFG''': This SFR determines which of the 16 pins with an analog input function (port B) is treated as an analog input or a DIO pin. The 16 most significant bits (high bits) AD1PCFG<31:16> are ignored, but AD1PCFG<15:0> determine which of the 16 pins is treated as an analog input. 0 indicates analog input, and 1 indicates DIO. So if the bit AD1PCFG<7> is 0, then the pin with the function AN7 is an analog input; if AD1PCFG<7> is 1, then it is a DIO. AD1PCFG resets to 0x0000, so all 16 pins of port B are treated as analog inputs by default. To make AN15 and AN1 analog inputs and the rest DIO, we can use the C command <tt>AD1PCFG = 0x7FFD</tt>. To make AN15 and AN1 analog inputs but leave the other settings unchanged, we can use the C command <tt>AD1PCFG &= 0x7FFD</tt>. Note we only have to specify 16 bits, or 4 hex digits, as the 16 most significant bits have no role. Instead of acting on the entire SFR, we could instead address an individual bit, using <tt>AD1PCFGbits.PCFG15 = 1</tt>, for example, to set the value of a single bit.		* '''AD1PCFG''': This SFR determines which of the 16 pins with an analog input function (port B) is treated as an analog input or a DIO pin. The 16 most significant bits (high bits) AD1PCFG<31:16> are ignored, but AD1PCFG<15:0> determine which of the 16 pins is treated as an analog input. 0 indicates analog input, and 1 indicates DIO. So if the bit AD1PCFG<7> is 0, then the pin with the function AN7 is an analog input; if AD1PCFG<7> is 1, then it is a DIO. AD1PCFG resets to 0x0000, so all 16 pins of port B are treated as analog inputs by default. To make AN15 and AN1 analog inputs and the rest DIO, we can use the C command <tt>AD1PCFG = 0x7FFD</tt>. To make AN15 and AN1 analog inputs but leave the other settings unchanged, we can use the C command <tt>AD1PCFG &= 0x7FFD</tt>. Note we only have to specify 16 bits, or 4 hex digits, as the 16 most significant bits have no role. Instead of acting on the entire SFR, we could instead address an individual bit, using <tt>AD1PCFGbits.PCFG15 = 1</tt>, for example, to set the value of a single bit.

	* '''TRISx''': This SFR determines which of the DIO pins of port x are inputs and which are outputs. For example, <tt>TRISBbits.TRISB5 = 0</tt> makes RB5 an output (0 = Output), <tt>TRISBbits.TRISB5 = 1</tt> makes RB5 an input (1 = Input), <tt>TRISB &= FF00</tt> makes RB0..RB7 outputs while leaving the others unchanged, <tt>TRISB ^= FF00</tt> makes RB8..RB15 inputs while leaving the others unchanged, and <tt>TRISB = FF00</tt> makes RB0..RB7 outputs and RB8..RB15 inputs.		* '''TRISx''': This SFR determines which of the DIO pins of port x are inputs and which are outputs. For example, <tt>TRISBbits.TRISB5 = 0</tt> makes RB5 an output (0 = Output), <tt>TRISBbits.TRISB5 = 1</tt> makes RB5 an input (1 = Input), <tt>TRISB &= FF00</tt> makes RB0..RB7 outputs while leaving the others unchanged, <tt>TRISB \|= FF00</tt> makes RB8..RB15 inputs while leaving the others unchanged, and <tt>TRISB = FF00</tt> makes RB0..RB7 outputs and RB8..RB15 inputs.

	* '''LATx''': A write to the latch chooses the output for pins configured as digital outputs. For example, <tt>LATB = 0x00FF</tt> makes pins RB0..RB7 high and pins RB8..RB15 low. An individual pin can be referenced using LATBbits.LATB13, for example.		* '''LATx''': A write to the latch chooses the output for pins configured as digital outputs. For example, <tt>LATB = 0x00FF</tt> makes pins RB0..RB7 high and pins RB8..RB15 low. An individual pin can be referenced using LATBbits.LATB13, for example.

Lynch: /* Details */

2011-01-26T09:16:52Z

Details

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	* '''CNPUE''': The relevant bits of this SFR are CNPUE<21:0>, and they apply only to the 22 change notification pins CN0..CN21. If CNPUEbits.CNPUE2 = 1, then the pin with CN2 function has the internal pull-up resistor enabled, and if CNPUEbits.CNPUE2 = 0, then it is disabled. The command <tt>CNPUE = 0xFFFFFF</tt> enables the internal pull-up resistors for all CN pins. The default has the pull-ups disabled.		* '''CNPUE''': The relevant bits of this SFR are CNPUE<21:0>, and they apply only to the 22 change notification pins CN0..CN21. If CNPUEbits.CNPUE2 = 1, then the pin with CN2 function has the internal pull-up resistor enabled, and if CNPUEbits.CNPUE2 = 0, then it is disabled. The command <tt>CNPUE = 0xFFFFFF</tt> enables the internal pull-up resistors for all CN pins. The default has the pull-ups disabled.

	Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a ~~CLEAR~~ register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB ^= 0x0001</tt>, but the former is faster.		Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB ^= 0x0001</tt>, but the former is faster.

	Other SFRs and their functions are described in Chapter 12 of the Reference Manual. The C names of the SFRs, and the structures with their bit references, can be found in the file p32mx795f512l.h, which is under pic32-libs/include/proc. The SET, CLR, and INV registers are described in Section 2 of the Reference Manual.		Other SFRs and their functions are described in Chapter 12 of the Reference Manual. The C names of the SFRs, and the structures with their bit references, can be found in the file p32mx795f512l.h, which is under pic32-libs/include/proc. The SET, CLR, and INV registers are described in Section 2 of the Reference Manual.

Lynch: /* Sample Code */

2011-01-26T09:13:52Z

Sample Code

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	</pre>		</pre>

	and try the program again with each. If you got the same results I did, you got a delay of about 11 seconds, 4 seconds, and just under 2 seconds, respectively, for the three cases. This indicates that just configuring the peripheral bus does nothing for us. This makes sense: in our bootloader, we already set both the system clock and the peripheral bus clock to 80 MHz, which is the maximum possible frequency for both. On the other hand, configuring the wait states gave us nearly a three times performance improvement. This means that this optimization reduced (from the default) the number of cycles the CPU waits for information requested from the flash memory. Finally, configuring the pre-fetch cache alone essentially gave us the entire speed-up. The pre-fetch cache stores recent instructions fetched from flash (program) memory and keeps it ready for use without flash wait states, and when possible, "runs ahead" to get future instructions so they are ready for the CPU without the flash wait cycles.		and try the program again with each. If you got the same results I did, you got a delay of about 11 seconds, 4 seconds, and just under 2 seconds, respectively, for the three cases. This indicates that just configuring the peripheral bus does nothing for us. This makes sense: in our bootloader, we already set both the system clock and the peripheral bus clock to 80 MHz, which is the maximum possible frequency for both. On the other hand, configuring the wait states gave us nearly a three times performance improvement. This means that this optimization reduced (from the default) the number of cycles the CPU waits for information requested from the flash memory. Finally, configuring the pre-fetch cache alone essentially gave us the entire speed-up. The pre-fetch cache stores recent instructions fetched from flash (program) memory and keeps them ready for use without flash wait states, and when possible, "runs ahead" to get future instructions so they are ready for the CPU without the flash wait cycles.

	== More Information ==		== More Information ==

Lynch: /* Library Functions */

2011-01-25T15:37:51Z

Library Functions

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	== Library Functions ==		== Library Functions ==

	The peripheral library offers a number of function calls to help you use the DIO pins. These functions have names such as <tt>PORTRead</tt>, <tt>PORTSetPinsDigitalIn</tt>, <tt>PORTSetPinsDigitalOut</tt>, etc. C source code can be found in pic32-libs/peripheral/ports/source/*.c, and .h header files can be found in pic32-libs/include/peripheral/ports.h. The DIO functions are simple enough, however, that we will usually just set the appropriate SFRs manually, as described above and demonstrated in the samples below.		The peripheral library offers a number of function calls to help you use the DIO pins. These functions have names such as <tt>PORTRead</tt>, <tt>PORTSetPinsDigitalIn</tt>, <tt>PORTSetPinsDigitalOut</tt>, etc. C source code can be found in pic32-libs/peripheral/ports/source/*.c, and .h header files can be found in pic32-libs/include/peripheral/ports.h. Documentation can be found in your MPLAB C32's doc directory, in Microchip-PIC32MX-Peripheral-Library.chm. The DIO functions are simple enough, however, that we will usually just set the appropriate SFRs manually, as described above and demonstrated in the samples below.

	== Sample Code ==		== Sample Code ==

Lynch: /* Details */

2011-01-25T15:34:13Z

Details

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	Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLEAR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB ^= 0x0001</tt>, but the former is faster.		Finally, each SFR (e.g., TRISB, LATD, PORTA, ODCC, etc.) has three more registers associated with it: a SET register, a CLEAR register, and an INV register. Writing to these registers allows atomic (single cycle) updating of the SFR contents, which is faster than reading the current value of the SFR, modifying it, and writing back to the SFR. SET means that bits are set (made equal to 1), CLR means that bits are cleared (made equal to 0), and INV means that bits are inverted. So <tt>TRISBCLR = 0x0110</tt> will clear bits 4 and 8 and <tt>TRISBSET = 0x0110</tt> will set bits 4 and 8. All other bits (with a 0 on the right-hand side of the = sign) are unchanged. For example, <tt>LATBSET = 0x0001</tt> has the same effect as <tt>LATB ^= 0x0001</tt>, but the former is faster.

	Other SFRs and their functions are described in Chapter 12 of the Reference Manual. The C names of the SFRs, and the ~~structrues~~ with their bit references, can be found in the file p32mx795f512l.h, which is under pic32-libs/include/proc. The SET, CLR, and INV registers are described in Section 2 of the Reference Manual.		Other SFRs and their functions are described in Chapter 12 of the Reference Manual. The C names of the SFRs, and the structures with their bit references, can be found in the file p32mx795f512l.h, which is under pic32-libs/include/proc. The SET, CLR, and INV registers are described in Section 2 of the Reference Manual.

	<!--		<!--

Lynch: /* Details */

2011-01-25T15:32:52Z

Details

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	* '''LATx''': A write to the latch chooses the output for pins configured as digital outputs. For example, <tt>LATB = 0x00FF</tt> makes pins RB0..RB7 high and pins RB8..RB15 low. An individual pin can be referenced using LATBbits.LATB13, for example.		* '''LATx''': A write to the latch chooses the output for pins configured as digital outputs. For example, <tt>LATB = 0x00FF</tt> makes pins RB0..RB7 high and pins RB8..RB15 low. An individual pin can be referenced using LATBbits.LATB13, for example.

	* '''PORTx''': <tt>val = PORTB</tt> returns the current digital inputs for DIO pins configured as inputs. PORTBbits.RB6 returns the digital input for RB6.		* '''PORTx''': <tt>val = PORTB</tt>, where val is an unsigned int, returns the current digital inputs for DIO pins configured as inputs. PORTBbits.RB6 returns the digital input for RB6.

	* '''ODCx''': <tt>ODCB = 0x00FF</tt> configures RB0..RB7 as open drain, and pins RB8..RB15 as typical buffered output. An individual pin can be referenced as ODCBbits.ODCB8, for example.		* '''ODCx''': <tt>ODCB = 0x00FF</tt> configures RB0..RB7 as open drain, and pins RB8..RB15 as typical buffered output. An individual pin can be referenced as ODCBbits.ODCB8, for example.

Lynch: /* Details */

2011-01-25T15:29:49Z

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	== Details ==		== Details ==

	The functions of the DIO pins are controlled by special function registers (SFRs). Each of these SFRs has 32 bits on the PIC32, but for many, ~~only~~ 16 ~~of the bits~~ are relevant. Depending on whether these bits are set to 0 or 1, different actions or settings are performed:		The functions of the DIO pins are controlled by special function registers (SFRs). Each of these SFRs has 32 bits on the PIC32, but for many, not all 32 are relevant. Depending on whether these bits are set to 0 or 1, different actions or settings are performed:

	* '''AD1PCFG''': This SFR determines which of the 16 pins with an analog input function (port B) is treated as an analog input or a DIO pin. The 16 most significant bits (high bits) AD1PCFG<31:16> are ignored, but AD1PCFG<15:0> determine which of the 16 pins is treated as an analog input. 0 indicates analog input, and 1 indicates DIO. So if the bit AD1PCFG<7> is 0, then the pin with the function AN7 is an analog input; if AD1PCFG<7> is 1, then it is a DIO. AD1PCFG resets to 0x0000, so all 16 pins of port B are treated as analog inputs by default. To make AN15 and AN1 analog inputs and the rest DIO, we can use the C command <tt>AD1PCFG = 0x7FFD</tt>. To make AN15 and AN1 analog inputs but leave the other settings unchanged, we can use the C command <tt>AD1PCFG &= 0x7FFD</tt>. Note we only have to specify 16 bits, or 4 hex digits, as the 16 most significant bits have no role. Instead of acting on the entire SFR, we could instead address an individual bit, using <tt>AD1PCFGbits.PCFG15 = 1</tt>, for example, to set the value of a single bit.		* '''AD1PCFG''': This SFR determines which of the 16 pins with an analog input function (port B) is treated as an analog input or a DIO pin. The 16 most significant bits (high bits) AD1PCFG<31:16> are ignored, but AD1PCFG<15:0> determine which of the 16 pins is treated as an analog input. 0 indicates analog input, and 1 indicates DIO. So if the bit AD1PCFG<7> is 0, then the pin with the function AN7 is an analog input; if AD1PCFG<7> is 1, then it is a DIO. AD1PCFG resets to 0x0000, so all 16 pins of port B are treated as analog inputs by default. To make AN15 and AN1 analog inputs and the rest DIO, we can use the C command <tt>AD1PCFG = 0x7FFD</tt>. To make AN15 and AN1 analog inputs but leave the other settings unchanged, we can use the C command <tt>AD1PCFG &= 0x7FFD</tt>. Note we only have to specify 16 bits, or 4 hex digits, as the 16 most significant bits have no role. Instead of acting on the entire SFR, we could instead address an individual bit, using <tt>AD1PCFGbits.PCFG15 = 1</tt>, for example, to set the value of a single bit.