Hwang: /* AND Gate */

2006-06-29T22:39:00Z

AND Gate

← Older revision		Revision as of 17:39, 29 June 2006
Line 4:		Line 4:
	==AND Gate==		==AND Gate==
	The symbol for the '''AND gate''':[[Image:AND_gate_symbol.gif]]		The symbol for the '''AND gate''':[[Image:AND_gate_symbol.gif]]

			Pins 1 and 2 are inputs, and pin 3 is the output.

	The AND gate will will output ''1'' if both inputs are also ''1''.		The AND gate will will output ''1'' if both inputs are also ''1''.

Hwang: /* NOR Gate */

2006-06-29T22:35:30Z

NOR Gate

← Older revision		Revision as of 17:35, 29 June 2006
Line 77:		Line 77:

	==NOR Gate==		==NOR Gate==
	Symbol for the NOR gate: [[Image:~~NOT_gate_symbol~~.gif]]		Symbol for the NOR gate: [[Image:NOR_gate_symbol.gif]]

	Similarly, the NOR gate is just an inverted OR gate. t will output ''1'' if neither of its inputs are ''1''.		Similarly, the NOR gate is just an inverted OR gate. t will output ''1'' if neither of its inputs are ''1''.

Hwang at 22:34, 29 June 2006

2006-06-29T22:34:05Z

New page

Digital circuits use Boolean logic to perform operations. Everything is in either one of two states: ''1'' (true) or ''0'' (false). Depending on your hardware, ''1'' usually corresponds to a high voltage and ''0'' corresponds to a low voltage.

__TOC__
==AND Gate==
The symbol for the '''AND gate''':[[Image:AND_gate_symbol.gif]]

The AND gate will will output ''1'' if both inputs are also ''1''.

{|border="1"
|+''Truth Table for AND Gate ''
|- align="center"
! colspan="2"| Inputs !! Output
|- align="center"
| 0 || 0 || 0
|- align="center"
| 0 || 1 || 0
|- align="center"
| 1 || 0 || 0
|- align="center"
| 1 || 1 || 1
|}

==OR Gate==
Symbol for the '''OR gate''': [[Image:OR_gate_symbol.gif]]

The OR gate will output ''1'' if any one or both of its inputs are ''1''.

{|border="1"
|+''Truth Table for OR Gate''
|- align="center"
! colspan="2"| Inputs !! Output
|- align="center"
| 0 || 0 || 0
|- align="center"
| 0 || 1 || 1
|- align="center"
| 1 || 0 || 1
|- align="center"
| 1 || 1 || 1
|}

==Inverter (NOT) Gate==
Symbol for the inverter: [[Image:Inverter_gate_symbol.gif]]

This is a '''NOT gate''', but in digital circuits it is usually called an '''inverter'''.

The OR gate will output ''1'' if its single input is ''0''.

{|border="1"
|+''Truth Table for OR Gate''
|- align="center"
!| Input !! Output
|- align="center"
| 0 || 1
|- align="center"
| 1 || 0
|}

==NAND Gate==
The symbol for the '''NAND gate''':[[Image:NAND_gate_symbol.gif]]

The NAND gate is simply an AND gate with an inverter at the output. Notice the "bubble" at the output node of the symbol; this bubble indicates an inverted output.

{|border="1"
|+''Truth Table for NAND Gate ''
|- align="center"
! colspan="2"| Inputs !! Output
|- align="center"
| 0 || 0 || 1
|- align="center"
| 0 || 1 || 1
|- align="center"
| 1 || 0 || 1
|- align="center"
| 1 || 1 || 0
|}

==NOR Gate==
Symbol for the NOR gate: [[Image:NOT_gate_symbol.gif]]

Similarly, the NOR gate is just an inverted OR gate. t will output ''1'' if neither of its inputs are ''1''.

{|border="1"
|+''Truth Table for NOR Gate ''
|- align="center"
! colspan="2"| Inputs !! Output
|- align="center"
| 0 || 0 || 1
|- align="center"
| 0 || 1 || 0
|- align="center"
| 1 || 0 || 0
|- align="center"
| 1 || 1 || 0
|}

==XOR==
Symbol for the '''XOR gate''': [[Image:XOR_gate_symbol.gif]]

The XOR (Exclusive OR) gate will output ''1'' if either of its inputs are ''1'', but ''not'' if both of its inputs are ''1''.

{|border="1"
|+''Truth Table for NOR Gate''
|- align="center"
! colspan="2"| Inputs !! Output
|- align="center"
| 0 || 0 || 0
|- align="center"
| 0 || 1 || 1
|- align="center"
| 1 || 0 || 1
|- align="center"
| 1 || 1 || 0
|}

==XNOR==
Symbol for the ''XNOR gate''': [[Image:XNOR_gate_symbol.gif]]

The XNOR gate is an inverted NOT gate; it will output ''1'' if neither of its inputs are ''1'', or if
''both'' of its inputs are ''1''.
{|border="1"
|+''Truth Table for XNOR Gate''
|- align="center"
! colspan="2"| Inputs !! Output
|- align="center"
| 0 || 0 || 1
|- align="center"
| 0 || 1 || 0
|- align="center"
| 1 || 0 || 0
|- align="center"
| 1 || 1 || 1
|}

Logic Gates - Revision history

Hwang: /* AND Gate */

Hwang: /* NOR Gate */

Hwang at 22:34, 29 June 2006