I2C communication between PICs - Revision history

Lynch at 13:48, 29 February 2008

2008-02-29T13:48:40Z

← Older revision		Revision as of 08:48, 29 February 2008
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	== Original Assignment ==

	Microcontrollers commonly talk to each other using protocols such as RS-232, SPI (for "serial peripheral interface"), I2C (or I^2C, "I squared C," for inter-integrated circuit), CAN bus, or other. This project is to demonstrate bidirectional I2C communication between two PICs. A demonstration might have the value of an analog input (potentiometer) at one PIC displayed as a "light bar" on the LEDs of the other PIC board, and simultaneously vice-versa.

	== Overview ==		== Overview ==

Matt Turpin: /* Overview */

2008-02-18T06:38:14Z

Overview

← Older revision		Revision as of 01:38, 18 February 2008
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	[http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf I2C] is pronounced "I squared C" and stands for Inter-Integrated Circuit. This protocol was designed by Phillips Semiconductors around 1992 to allow easy communication between components on the same circuit board and can achieve transfer rates of up to 400 kbit/sec. Is is a 2 line (plus common ground) communication method for one master device to control up to 112 slave devices. While it is possible to have multiple masters on the same I2c bus, this page will only deal with a one master configuration.		[http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf I2C] is pronounced "I squared C" and stands for Inter-Integrated Circuit. This protocol was designed by Phillips Semiconductors around 1992 to allow easy communication between components on the same circuit board and can achieve transfer rates of up to 400 kbit/sec. Is is a 2 line (plus common ground) communication method for one master device to control up to 112 slave devices. While it is possible to have multiple masters on the same I2c bus, this page will only deal with a one master configuration.

	The two lines are named SCL and SDA where SCL is the CLock line and SDA is the DAta line. The PIC 4520 is designed to use pin 18 as SCL and pin 23 as SDA for hardware I2C. Note that pin 18 is one of the only pins not accessible on the prototyping board. An additional wire can be added as shown in the example image. I2C requires the lines to be high unless the master or the slave is pulling the line down, so you will need to use pull up resistors on both the clock and data lines.		The two lines are named SCL and SDA where SCL is the CLock line and SDA is the DAta line. The PIC 4520 is designed to use pin 18 as SCL and pin 23 as SDA for hardware I2C. Note that pin 18 is one of the only pins not accessible on the prototyping board. An additional wire can be added as shown in the example image. It is possible to use lines accessible from the prototyping board to communicate via software I2C, but this has data rates of less than one fourth those of hardware I2C and will therefore be omitted. I2C requires the lines to be high unless the master or the slave is pulling the line down, so you will need to use pull up resistors on both the clock and data lines.

	An communication diagram is shown:		An communication diagram is shown:

Matt Turpin at 06:15, 18 February 2008

2008-02-18T06:15:48Z

← Older revision		Revision as of 01:15, 18 February 2008
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	== Overview ==		== Overview ==

	I2C is pronounced "I squared C" and stands for Inter-Integrated Circuit. Is is a 2 line (plus common ground) communication method for one master device to control up to 112 slave devices. While it is possible to have multiple masters on the same I2c bus, this page will only deal with a one master configuration.		[http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf I2C] is pronounced "I squared C" and stands for Inter-Integrated Circuit. This protocol was designed by Phillips Semiconductors around 1992 to allow easy communication between components on the same circuit board and can achieve transfer rates of up to 400 kbit/sec. Is is a 2 line (plus common ground) communication method for one master device to control up to 112 slave devices. While it is possible to have multiple masters on the same I2c bus, this page will only deal with a one master configuration.

	The two lines are named SCL and SDA where SCL is the CLock line and SDA is the DAta line. The PIC 4520 is designed to use pin 18 as SCL and pin 23 as SDA for hardware I2C. Note that pin 18 is one of the only pins not accessible on the prototyping board. An additional wire can be added as shown in the example image. I2C requires the lines to be high unless the master or the slave is pulling the line down, so you will need to use pull up resistors on both the clock and data lines.		The two lines are named SCL and SDA where SCL is the CLock line and SDA is the DAta line. The PIC 4520 is designed to use pin 18 as SCL and pin 23 as SDA for hardware I2C. Note that pin 18 is one of the only pins not accessible on the prototyping board. An additional wire can be added as shown in the example image. I2C requires the lines to be high unless the master or the slave is pulling the line down, so you will need to use pull up resistors on both the clock and data lines.
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	}		}
	}		}

			==More Information==

			Phillips Brief on I2c: http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf

			An I2C Primer: http://www.i2c-bus.org/I2C-Primer.520.0.html

Matt Turpin: /* Two Way Communication */

2008-02-18T06:05:21Z

Two Way Communication

← Older revision		Revision as of 01:05, 18 February 2008
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	== Two Way Communication ==		== Two Way Communication ==

	An alternate circuit diagram is shown below.		An alternate circuit diagram is shown below with an analogue input on the slave and three switches.

	[[image:I2C_Alternate_Circuit_Diagram\|center\|600px]]		[[image:I2C_Alternate_Circuit_Diagram\|center\|600px]]
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	{		{

	~~the~~ first command bit is empty, so nothing is done.		The first command bit is empty, so nothing is done.

	if(state == 0)		if(state == 0)

Matt Turpin: /* Code */

2008-02-18T05:50:42Z

Code

← Older revision		Revision as of 00:50, 18 February 2008
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	#use I2C(FAST, SCL=PIN_C3, SDA=PIN_C4, FORCE_HW) //using hardware I2C, built into the PIC, make sure to include this line in any master I2C program		#use I2C(FAST, SCL=PIN_C3, SDA=PIN_C4, FORCE_HW) //using hardware I2C, built into the PIC, make sure to include this line in any master I2C program

			To communicate with a device, we use the following lines of code where 0x14 is the device name. The first line is the issuing of the start command and this forces all slave devices on the bus to wait for their address. The next write command is the address of the slave. The following byte is the data being sent to the slave. All communication must terminate with a stop command or the line will remain open and no future communication is possible until the command is given.
	To communicate with a device, we use the following lines of code where 0x14 is the device name.

	i2c_start(); //begin transmission		i2c_start(); //begin transmission
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	void sspinterupt()		void sspinterupt()
	{		{

			The definition of state is to determine whether or not the master is requesting or sending data.

	state = i2c_isr_state(); //Reading the type of transmission		state = i2c_isr_state(); //Reading the type of transmission

			State is less than 0x80 for all read operations.

	if(state < 0x80) //Master is sending data		if(state < 0x80) //Master is sending data
	{		{
	data = i2c_read(); //An array will be needed to store data if more than one byte is transferred		data = i2c_read(); //An array will be needed to store data if more than one byte is transferred
	}		}

			State will be equal to 0x80 for write commands.

	if(state == 0x80) //Master is requesting data		if(state == 0x80) //Master is requesting data
	{		{

Matt Turpin: /* Overview */

2008-02-18T03:12:53Z

Overview

← Older revision		Revision as of 22:12, 17 February 2008
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	I2C is pronounced "I squared C" and stands for Inter-Integrated Circuit. Is is a 2 line (plus common ground) communication method for one master device to control up to 112 slave devices. While it is possible to have multiple masters on the same I2c bus, this page will only deal with a one master configuration.		I2C is pronounced "I squared C" and stands for Inter-Integrated Circuit. Is is a 2 line (plus common ground) communication method for one master device to control up to 112 slave devices. While it is possible to have multiple masters on the same I2c bus, this page will only deal with a one master configuration.

	The two lines are named SCL and SDA where SCL is the CLock line and SDA is the DAta line. The PIC 4520 is designed to use pin 18 as SCL and pin 23 as SDA for hardware I2C. Note that pin 18 is one of the only pins not accessible on the prototyping board. An additional wire can be added as shown ~~below~~.		The two lines are named SCL and SDA where SCL is the CLock line and SDA is the DAta line. The PIC 4520 is designed to use pin 18 as SCL and pin 23 as SDA for hardware I2C. Note that pin 18 is one of the only pins not accessible on the prototyping board. An additional wire can be added as shown in the example image. I2C requires the lines to be high unless the master or the slave is pulling the line down, so you will need to use pull up resistors on both the clock and data lines.

	An ~~example~~ communication diagram is shown ~~below~~		An communication diagram is shown:

	[[image:I2C_Data_Transfer.jpg\|center]]		[[image:I2C_Data_Transfer.jpg\|center]]
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	* S - As the master pulls down the data line, the falling edge of the data line signifies the start condition.		* S - As the master pulls down the data line, the falling edge of the data line signifies the start condition.
	* P - As the master allows the data line to rise, the rising edge of the data line signifies the stop condition.		* P - As the master allows the data line to rise, the rising edge of the data line signifies the stop condition.
			* B - Individual bits being transferred.

	The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.		The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.

Matt Turpin: /* Overview */

2008-02-18T03:02:16Z

Overview

← Older revision		Revision as of 22:02, 17 February 2008
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	[[image:I2C_Data_Transfer.jpg\|center]]		[[image:I2C_Data_Transfer.jpg\|center]]

	S - As the master pulls down the data line, the falling edge of the data line signifies the start condition.		* S - As the master pulls down the data line, the falling edge of the data line signifies the start condition.
	P - As the master allows the data line to rise, the rising edge of the data line signifies the stop condition.		* P - As the master allows the data line to rise, the rising edge of the data line signifies the stop condition.

	The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.		The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.

Matt Turpin: /* Overview */

2008-02-18T03:01:51Z

Overview

← Older revision		Revision as of 22:01, 17 February 2008
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	[[image:I2C_Data_Transfer.jpg\|center]]		[[image:I2C_Data_Transfer.jpg\|center]]

			S - As the master pulls down the data line, the falling edge of the data line signifies the start condition.
	S - Start condition; P - Stop condition; B - One bit transferred
			P - As the master allows the data line to rise, the rising edge of the data line signifies the stop condition.

	The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.		The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.

Matt Turpin: /* Overview */

2008-02-18T02:59:22Z

Overview

← Older revision		Revision as of 21:59, 17 February 2008
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	[[image:I2C_Data_Transfer.jpg\|center]]		[[image:I2C_Data_Transfer.jpg\|center]]

	S - Start condition; P - Stop condition; B - One bit transferred~~; data changes allowed when clock low (blue)~~		S - Start condition; P - Stop condition; B - One bit transferred

			The data line can only change while the clock line is low. The data line is only read when the clock line is high and therefore 1 bit can be transferred per cycle of the clock line.

	The master is initially sends a start bit followed by the 7-bit address of the slave it wishes to communicate with. The next bit represents whether it wishes to write(0) to or read(1) from the slave.		The master is initially sends a start bit followed by the 7-bit address of the slave it wishes to communicate with. The next bit represents whether it wishes to write(0) to or read(1) from the slave.

Matt Turpin: /* Circuit */

2008-02-11T17:38:00Z

Circuit

← Older revision		Revision as of 12:38, 11 February 2008
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	== Circuit ==		== Circuit ==

	Below is a simple circuit diagram showing the master PIC with 2 close button switches. Note that pin 18 (RC3) is not brought out to the circuit board, but a wire can be soldered next to the PIC itself.		Below is a simple circuit diagram showing the master PIC with 2 close button switches. Note that pin 18 (RC3) is not brought out to the circuit board, but a wire can be soldered next to the PIC itself. Both SDA and SCL need pull up resistors as either the master or the slave can hold the line low to stop communication.
	[[image:I2C Circuit Diagram.jpg\|center\|600px]]		[[image:I2C Circuit Diagram.jpg\|center\|600px]]


	Here is an example of how to wire this.		Here is an example image of how to wire this.
	[[image:I2C Wiring Image.jpg\|center\|600px]]		[[image:I2C Wiring Image.jpg\|center\|600px]]