Flip-Flops and Latches - Revision history

Hwang: /* Asynchonous Inputs */

2006-07-03T18:56:16Z

Asynchonous Inputs

Hwang: /* Asynchonous Inputs */

2006-07-03T18:56:03Z

Asynchonous Inputs

Hwang: /* Asynchonous Inputs */

2006-07-03T18:55:43Z

Asynchonous Inputs

Hwang: /* Latches */

2006-06-30T21:15:01Z

Latches

Hwang at 21:03, 30 June 2006

2006-06-30T21:03:30Z

Hwang: /* D flip-flop */

2006-06-30T20:46:55Z

D flip-flop

Hwang: /* JK flip-flop */

2006-06-30T20:45:38Z

JK flip-flop

Hwang at 20:43, 30 June 2006

2006-06-30T20:43:20Z

Hwang: /* J-K flip-flop */

2006-06-30T20:35:05Z

J-K flip-flop

Hwang: /* D flip-flop */

2006-06-30T20:29:52Z

D flip-flop

@@ Line 10: / Line 10: @@
 ==Asynchonous Inputs==
-Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ([[Digital#Active_Low_Input Active Low Input]]).  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.
+Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ([[Digital#Active_Low_Input|Active Low Input]]).  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.
 The symbols used for ''clear'' and ''preset'' (the bubble indicates an inverted signal):

@@ Line 10: / Line 10: @@
 ==Asynchonous Inputs==
-Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ([[Digital#Active_Low_Input]]).  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.
+Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ([[Digital#Active_Low_Input Active Low Input]]).  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.
 The symbols used for ''clear'' and ''preset'' (the bubble indicates an inverted signal):

@@ Line 10: / Line 10: @@
 ==Asynchonous Inputs==
-Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ('''active low input''').  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.
+Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ([[Digital#Active_Low_Input]]).  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.
 The symbols used for ''clear'' and ''preset'' (the bubble indicates an inverted signal):

@@ Line 98: / Line 98: @@
 The most common type of latch is the '''D latch'''.  While CK is high, Q will take whatever value ''D'' is at.  When CK is low, ''Q'' will latch onto the last value it had before CK went low, and hold it until CK goes high again.
+Timing diagram for the D latch:
+[[Image:d_latch_timing.gif]]

@@ Line 1: / Line 1: @@
-Flip-flops are a useful type of digital device that can store binary states, or be used as a sort of digital toggle switch.  The flip-flop is a digital device, so its output (labeled with a ''Q'' in schematic diagrams) will take on the value of either 1 (high) or 0 (low).  Many flip-flops will also provide the '''complementary''' output (an inverted output).
+Flip-flops are a useful type of digital device that can store binary states, or be used as a sort of digital toggle switch.  Flip-flops can be built up from distinct logic gates, but they can easily be bought in packaged chips.  The flip-flop is a digital device, so its output (labeled with a ''Q'' in schematic diagrams) will take on the value of either 1 (high) or 0 (low).  Many flip-flops will also provide the '''complementary''' output (an inverted output).
 __TOC__
@@ Line 35: / Line 35: @@
 Symbol for the D flip-flop:[[Image:D_flipflop_symbol.gif]]
-The D flip-flop has an input ''D'', and the output ''Q'' will take on the value of ''D'' at every triggering edge of the clock pulse and hold it until the next triggering pulse.  The D flip-flop is usually ''positive edge triggered''.
+The D (Data) flip-flop has an input ''D'', and the output ''Q'' will take on the value of ''D'' at every triggering edge of the clock pulse and hold it until the next triggering pulse.  The D flip-flop is usually ''positive edge triggered''.
 The truth table for a positive edge triggered D flip-flop:
@@ Line 93: / Line 93: @@
 [[Image:JK_flipflop_timing.gif]]
+==Latches==
+Latches are similar to flip-flops, but instead of being '''edge triggered''', they are '''level triggered'''.
+The most common type of latch is the '''D latch'''.  While CK is high, Q will take whatever value ''D'' is at.  When CK is low, ''Q'' will latch onto the last value it had before CK went low, and hold it until CK goes high again.

@@ Line 46: / Line 46: @@
 | 1 || &uarr; || 1
 |- align="center"
-| X || 0  || Q<sub>0</sub>
+| X || 0,1  || Q<sub>0</sub>
-|- align="center"
-| X || 1  || Q<sub>0</sub>
 |}
 (&uarr; indicates a rising edge on the clock pulse; '''X''' indicates that it has no effect on outcome)

@@ Line 62: / Line 62: @@
 At the triggering edge:
 If ''J'' is 1 and ''K'' is 0, ''Q'' is 1.
@@ Line 74: / Line 72: @@
 The JK flip-flop is usually ''negative edge triggered''.
 The truth table for a negatively triggered JK flip-flop:
@@ Line 91: / Line 90: @@
 | X || X || 0,1 || Q<sub>0</sub>
 |}
+The timing diagram for the negatively triggered JK flip-flop:
+[[Image:JK_flipflop_timing.gif]]

@@ Line 16: / Line 16: @@
 [[Image:clr_pre_symbol.gif]]
-{|border="1"
+{|border="1" cellpadding="5"
 |+''Truth Table for CLR and PRE (active low)''
 |- align="center"
@@ Line 38: / Line 38: @@
 The truth table for a positive edge triggered D flip-flop:
-{|border="1"
+{|border="1" cellpadding="5"
 |- align="center"
 ! D !! CK !!Q
@@ Line 62: / Line 62: @@
 At the triggering edge:
 If ''J'' is 1 and ''K'' is 0, ''Q'' is 1.
@@ Line 74: / Line 76: @@
 The truth table for a negatively triggered JK flip-flop:
+{|border="1" cellpadding="5"
+|- align="center"
+! J !! K !! CK !! Q
+|- align="center"
+| 0 || 0 || &darr; || Q<sub>0</sub>
+|- align="center"
+| 0 || 1 || &darr; || 0
+|- align="center"
+| 1 || 0 || &darr; || 1
+|- align="center"
+| 1 || 1 || &darr; || Q'<sub>0</sub>
+|- align="center"
+| X || X || 0,1 || Q<sub>0</sub>
+|}

@@ Line 56: / Line 56: @@
 [[Image:D_flipflop_timing.gif]]
-===J-K flip-flop===
+===JK flip-flop===
 Symbol for the JK flip-flop: [[Image:JK_flipflop_symbol.gif]]
-The JK flip-flop has two inputs, labeled ''J'' and ''K''.  ''J'' corresponds to a "set" signal, and ''K'' corresponds to a "reset" signal.  The JK flip-flop is usually ''negative edge triggered''.
+The JK flip-flop has two inputs, labeled ''J'' and ''K''.  ''J'' corresponds to a "set" signal, and ''K'' corresponds to a "reset" signal.
+At the triggering edge:
+If ''J'' is 1 and ''K'' is 0, ''Q'' is 1.
+If ''J'' is 0 and ''K'' is 1, ''Q'' is 0.
+If ''J'' and ''K'' are both 0, the output stays the same as it was before.
+If ''J'' and ''K'' are both 1, the output is inverted.
+The JK flip-flop is usually ''negative edge triggered''.
+The truth table for a negatively triggered JK flip-flop: