View source for Flip-Flops and Latches

Flip-flops are a useful type of digital device that can store binary states, or be used as a sort of digital toggle switch.  The flip-flop is a digital device, so its output (labeled with a ''Q'' in schematic diagrams) will take on the value of either 1 (high) or 0 (low).  Many flip-flops will also provide the '''complementary''' output (an inverted output).

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==Edge Triggering==
Because the state of a flip-flop often depends on the previous state of a circuit (for example, the output of one flip flop may be the input to another), and because each flip-flop and logic gate needs a certain amount of time to switch its output, we usually '''clock''' the devices, that is, we synchonize all the flip-flops to change states at the same time with a clocked pulse.  Flip-flops are '''edge triggered'''; they either change states when the clock goes from 0 to 1 (positive/rising edge) or  when the clock goes from 1 to 0 (negative/falling edge).

The symbols used for positive and negative edge triggering on flip-flops:

[[Image:edge_triggering_symbol.gif]]

==Asynchonous Inputs==
Many flip-flops will also have a '''clear''' (CLR) and '''preset''' (PRE) terminal.  These inputs are typically inverted, so they are active when the input signal is ''low'' ('''active low input''').  The CLR and PRE signals can be asserted any time and don't have to be edge triggered; they will override any other inputs, including the clock.

The symbols used for ''clear'' and ''preset'' (the bubble indicates an inverted signal):

[[Image:clr_pre_symbol.gif]]

{|border="1" 
|+''Truth Table for CLR and PRE (active low)'' 
|- align="center"
! PRE !! CLR !! Output 
|- align="center"
| 0 || 0 || Error state
|- align="center"
| 0 || 1 || 1
|- align="center"
| 1 || 0 || 0  
|- align="center"
| 1 || 1 || Depends on inputs and clock
|}

==Types of flip-flops==
There are several types of flip-flops but the two most important kind are the D and J-K flip-flops.
===D flip-flop===
Symbol for the D flip-flop:[[Image:D_flipflop_symbol.gif]]

The D flip-flop has an input ''D'', and the output ''Q'' will take on the value of ''D'' at every triggering edge of the clock pulse and hold it until the next triggering pulse.  The D flip-flop is usually positive edge triggered.

Timing diagram for the positive edge triggered D flip-flop:

[[Image:D_flipflop_timing.gif]]

===J-K flip-flop===