1. (True/False) The CPU is processing an interrupt at priority 5,
sub-priority 0.  Another interrupt request is generated at priority 5,
sub-priority 2.  The CPU suspends its current ISR and attends to the
new ISR.   True or false?
ANS:  False.  Since it is the same priority, the new interrupt must wait.

2. Explain in a sentence "context save and restore."
ANS:  Before the CPU executes an ISR, it saves its current registers
to  RAM, and when it finishes, it copies them back, so it can begin
executing again where it left off.

3. Explain in a sentence the shadow register set.
ANS:  This is an extra set of registers in the CPU that the CPU can
switch to while executing an ISR, preventing it from having to do a
context  save and restore.

4. Explain in a sentence the difference between single vector and
multi-vector interrupt modes.
ANS:  In single-vector mode, there is only one ISR that is invoked by
all  interrupts, and in multi-vector mode, there are many possible
ISRs  that could be executed, depending on the IRQ.

5. There are 3 IFS registers (IFS0-2), 3 IEC registers (IEC0-2), and
16 IPC  registers (IPC0-15).

(a) What are the IFS registers used for?
ANS:  The bits of the Interrupt Flag Status register contain a 1 if
that interrupt  has been requested, and a 0 if not.

(b) What are the IEC registers used for?
ANS:  The bits of the Interrupt Enable Control register contain a 1 if
that interrupt  is enabled and a 0 if not.

(c) What are the IPC registers used for?
ANS:  Bits in the Interrupt Priority Control registers specify the
priority and sub-priority  levels of the various interrupts.