Using the LS7366R SPI Quadrature Counter

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(New page: ==Introduction== The [ LS7366R] is a powerful decoder/counter chip which can be connected directly to a motor encoder to count encoder pul...)
(Overview of the LS7366R)

Revision as of 17:49, 2 May 2010



The LS7366R is a powerful decoder/counter chip which can be connected directly to a motor encoder to count encoder pulses. The 7366 stores a current count of the pulses, which can be read by the PIC via SPI at any time. This is in contrast with the LS7166, which uses a parallel bus to communicate with the PIC. By using the 7366, the PIC can keep track of a motor's current position without devoting any onboard resources to tracking pulses. The 7366 can be configured to store the count as a 1-4 byte number, depending on the application.

The code on this page is for the PIC32.

Overview of the LS7366R

The LS7366R is a 32-bit counter. In quadrature mode the counter can be directly connected to the A and B channels of a motor encoder and will count pulses as they arrive. The counter register can be configured to be 1, 2, 3, or 4 bytes wide, so that if the application needs less than 32 bits transmission times can be reduced. In "modulo-n" mode the counter will remain in a given range, which can be set to the number of pulses in a full rotation so that a read from the counter will result in the exact position of the motor without need for additional calculations.

The 7366 is connected to the PIC via a 4 wire SPI bus. Three of the wires, SCK, SDI, and SDO, can be shared with other SPI devices. The /SS (slave select) line must be dedicated to the 7366. A series of communication actions results in a particular internal register being read from or written to. The registers are for control, status, and output functions. Although mostly handled by the library code, here is a description of each register:

  • MDR0- "Mode Regiser 0", the first control register which controls the quadrature mode, counting mode, index mode, and more
  • MDR1- "Mode register 1", the second control register controlling the number of bytes the counter will use and the flags
  • DTR- The value of DTR can be transferred to the counter register (CNTR) under software or hardware control. This is were the high count value is stored for modulo-n mode.
  • CNTR- Counter register which stores the current count. This register cannot be read from directly. Instead, a read will trigger a copy from CNTR to OTR, then OTR will be read.
  • OTR- This register is used to store the value copied from CNTR for output. Note that reading from CNTR will automatically use OTR, and reading from OTR manually will read the value of CNTR at the time of the last CNTR read.
  • STR- This is a status register containing status bits
  • IR- This register is used internally to select the register being written to or read from on the next bus transaction.

Note that after setup the only registers the user should generally be referencing are CNTR (count), and STR (status) if needed.



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