NU32v2: A Detailed Look at Programming the PIC32

** This page is under construction and is not complete. KML 1/17/2011. **

After you have programmed your PIC32 for the first time and verified that you can create a new project, compile it, and run it on your NU32v2, it is useful to take a step back and understand the basics of the programming process, beginning with a PIC32 fresh from the factory. We will do that on this page. We will begin by discussing the virtual memory map of the PIC32. To discuss the virtual memory map, it is useful to know hexadecimal (hex, or base 16) notation, where each digit of a hex number takes one of 16 values, 0...9, A...F. Since 16 = 2^4, a single hex digit represents four digits of a number written in binary (base 2). The table below gives examples.

Hex	Binary	Base 10
7	0111	7
D	1101	13
B5	1011 0101	181

To distinguish hex and binary numbers from base 10 numbers, we begin the numbers with 0x and 0b, respectively. For example, 0xA9 = 10*16^1 + 9*16^0 = 0b10101001 = 1*2^7 + 0*2^6 + 1*2^5 + 0*2^4 + 1*2^3 + 0*2^2 + 0*2^1 + 1*2^0 = 160 = 1*10^2 + 6*10^1 + 0*10^0. The 0x and 0b conventions are also used in the C language.

The PIC32 Virtual Memory Map

The PIC32 has a virtual memory map consisting of 4 GB (four gigabytes, or 2^32 bytes, where each byte equals 8 bits) of addressable memory. All memory regions reside in this virtual memory space at their unique respective addresses. This includes program memory (flash), data memory (RAM), peripheral special function registers (SFRs), etc. For example, the peripheral SFRs begin at virtual memory location 0xBF800000 and end at virtual memory address 0xBF8FFFFF. Subtracting the begin address from the end address, and adding one byte, we get 0x100000, which is 1*16^5 = 1,048,576, commonly written as 1 MB. (Note: Section 3 of the reference manual incorrectly indicates that the size of this region is 4 KB.)

In addition to this virtual memory map, there is also a physical memory map. When you are writing a program, you only deal with the virtual memory map. The PIC implements a Fixed Mapping Translation (FMT) unit that takes the virtual memory address and maps it to a physical memory address. In other words, the virtual memory address is translated to a set of bit values on an addressing bus that allows the PIC's CPU to address the appropriate peripheral, flash memory location, RAM location, etc. We will focus on the virtual memory map, not the physical memory map, since our goal is to program the PIC and we don't need to concern ourselves with the FMT. (On the other hand, peripherals that access memory independently of the CPU, such as for DMA [direct memory access], must use physical addresses. To learn more about physical addresses, see Section 3 of the PIC32 Family Reference Manual.)

Virtual memory is partitioned into two types of address space: user address space (the lower 2 GB) and kernel address space (the upper 2 GB). By analogy to your personal computer, the kernel address space is to hold the computer's operating system, while the user address space is to hold a program that runs under the operating system. This is for safety: the user's program should not interfere with or compromise the operating system, i.e., it shouldn't be able to overwrite data that the operating system needs to function. We will not be using an operating system, so our programs will reside in the kernel address space.

The kernel virtual address space contains two subsections: one that is cacheable and one that is not. "Cacheable" means that information is stored in the cache by the prefetch cache module, which speeds up execution by limiting wait states when fetching data or instructions from flash. The prefetch cache module is activated when we execute the command SystemConfigPerformance().

The three major partitions of PIC32 virtual memory, then, are called KSEG0, KSEG1, and USEG/KUSEG, where KSEG0 corresponds to the cacheable kernel address space, KSEG1 corresponds to the non-cacheable kernel address space, and USEG/KUSEG corresponds to the user address space. The "K" in this last name indicates that programs in the kernel can address the user address space. Programs in the user address space cannot access the kernel address space.

Each of KSEG0, KSEG1, and USEG/KUSEG are further broken into the following sections: program flash, data RAM, and program RAM. The PIC may be made to run a program that is stored in RAM (as opposed to the usual case of a program stored in flash), which is why we have this last category.

Finally, we have two more areas of kernel memory for (1) the peripheral SFRs and (2) boot flash, the code that is executed upon reset of the PIC.

The virtual memory map is summarized in the table below:

Start Address	Size (bytes)	Partition	Kind	Notes
0x7D000000 + BMXPUPBA	BMXPFMSZ - BMXPUPBA	USEG/KUSEG	program flash
0x7F000000	BMXDUPBA - BMXDUDBA	USEG/KUSEG	data RAM
0x7F000000	BMXDRMSZ - BMXDUPBA	USEG/KUSEG	program RAM
0x80000000	BMXDKPBA	KSEG0 (cacheable)	data RAM	same physical address as KSEG1 data RAM
0x80000000 + BMXDKPBA	BMXDUDBA - BMXDKPBA	KSEG0 (cacheable)	program RAM	same physical address as KSEG1 program RAM
0x9D000000	BMXPUPBA	KSEG0 (cacheable)	program flash	same physical address as KSEG1 program flash
0xA0000000	BMXPUPBA	KSEG1	data RAM
0xA0000000 + BMXDKPBA	BMXDUDBA - BMXDKPBA	KSEG1	program RAM
0xBD000000	BMXPUPBA	KSEG1	program flash
0xBF800000	1 MB	kernel (KSEG1)	peripheral SFRs
0xBFC00000	12 KB	kernel	boot flash

In the table above, BMXPFMSZ and BMXDRMSZ are read-only registers containing the size of the program flash (512 K for us) and data RAM (128 K for us). The registers BMXqBA stand for "bus matrix" (BMX) and "base address offset" (BA), where q = PUP is for the user's segment of program flash, q = DUP is for the user's program space in RAM, q = DUD is for the user's data space in RAM, and q = DK is for the kernel program space in RAM. In our programs, we do not need to set the BMX registers. Leaving them at their default values allows maximum RAM and flash for kernel mode applications. If we want to run code from RAM or set up a user mode partition, we need to configure the BMX registers.

When the PIC is reset, it goes to the reset address 0xBFC00000, which is the location of the boot flash.

Programming a PIC32 with a Programmer

here describe how programming usually works with a programmer, then say we just use it to put a bootloader on the PIC32, so we only have to use a USB cable in future. makes it economically feasible to do mechatronics outside the lab (don't need to buy a programmer for everyone)

The PIC32 Bootloader

say something about the crt0 code at reset. (stored at 0xBFC00000?) what's the default when we write a program and load it using the programmer? what happens when we put our own bootloader on? does it go in the space where the crt0 code used to be?

DiJasio talks about crt0 on p. 59. Mentions defining _on_reset() to do anything time critical before crt0 finishes executing. one function of crt0 is to fill statically allocated arrays with zeros in RAM, or to copy from flash to RAM any statically allocated initialized arrays.

give the bootloader code, say what it does. anything related to the memory partitioning?

Programming a PIC32 Loaded with a Bootloader

give the Processing code, say what it does generally, how it works with the bootloader on the PIC.

Creating a .hex File from the MPLAB IDE

procdefs.ld, and what it does

your C program

the .c and .h files it includes: NU32v2.h (configuration bits, any simple mnemonics), plib.h, drill down to addresses in the virtual memory map (above)

definition of heap size, optimization level, etc., will still be done in IDE, correct? can all choices be seen in one place somehow (e.g., a makefile or something), or do we have to use the GUI to search through each set of options individually?

mention .a files (libraries, no source code?)

what is the search path for finding .h and .c files? seems we have some of the same library names under MPLAB C32 and MPLAB C32 Suite; which does our compiler find?